在當今的DSP 系統(tǒng)中，作為聯(lián)系模擬世界與強大的數(shù)字領域的橋梁，ADC 演了重要的角色。由于Sigma-Delta ADC 很好地折衷了轉換器的速度和精度，因此成為了用于通信
系統(tǒng)中ADC 的極佳選擇。本文采用了2-1-1 結構實現(xiàn)4 階調制器，設計了一個全差分增益
提高Telescopic 運算放大器，用于第一級積分器。采用了0.6μmN-Well CMOS 工藝下加以模擬，電源電壓為3v 時，功耗為39Mw,調制器的信噪比達到87.3DB.
關鍵詞：Σ-Δ 調制器；級聯(lián)結構；跨導運算放大器；非理想因素
Abstract: ADCs fulfill an important role as the link between the analog world and the powerful
digital processing environment in today’s DSP systems. Among the wide variety of ADC
architectures, Sigma-Delta ADC is an optimum candidate to meet the performance requirements of communication systems because it provides an efficient way of trading off speed for resolution. In this paper, the 4th-order modulator has been implemented with a 2-1-1 Cascaded Structure .A fully differential telescopic OTA with gain enhancement has been designed for the first integrator, the modulator is implemented with fully differential switched capacitor circuits. In 0.6μmN-Well CMOS process with a 3v power supply and dissipates about 39 Mw, The modulator achieves SNR of 87.3DB.
Keywords: Sigma-delta modulator； Cascade architecture； OTA；Non-ideality