//有限狀態(tài)機(jī)分割設(shè)計(jì)，其實(shí)質(zhì)就是一個(gè)狀態(tài)機(jī)分割成多個(gè)狀態(tài)機(jī)，或者說(shuō)多個(gè)
//狀態(tài)機(jī)的協(xié)同設(shè)計(jì)來(lái)實(shí)現(xiàn)一個(gè)較為復(fù)雜的狀態(tài)跳轉(zhuǎn)設(shè)計(jì)，例如說(shuō)玩游戲的一個(gè)
//狀態(tài)跳轉(zhuǎn)，玩家 A 操作的時(shí)候是一種狀態(tài)，玩家 B 操作的時(shí)候又是另外的一
//種狀態(tài)。
`timescale 1ns / 1ps


//
// Company: 
// Engineer: 
//
// Create Date: 2018/11/02 10:14:11
// Design Name: 
// Module Name: FSM_div
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module FSM_div(
clk, X, rst, Z,state1,state2
);
    input clk, X, rst;
    output Z;
    parameter S0 = 2'b00, S1= 2'b01,
    S2 = 2'b10,SA = 2'b11, S3 = 2'b00, S4 = 2'b01,
    S5 = 2'b10,SB = 2'b11;
    output reg [1:0] state1,state2;
    reg [1:0] next_state1,next_state2;


    always @( posedge clk )begin
        if(rst) begin
            state1 <= S0;state2<=SB;end
        else begin
            state1 <= next_state1;
            state2 <= next_state2;end
            end


        always @(state1 or X) begin
        case(state1)
        S0:begin if(X) next_state1<=S1;
                  else next_state1<=S0;end
        S1:begin if(X) next_state1<=S1;
                  else next_state1<=S2;end
        S2:begin if(X) next_state1<=S1;
                  else next_state1<=SA;end
        SA:begin if(X)
                    begin
                        if(state2==S4 || state2==S5)
                        next_state1<=S1;
                        else next_state1<=SA;
                    end
                 else if(state2==S3)
                 next_state1<=S0;
                 else next_state1<=SA;
                 end
         endcase
         end
     always @(state1 or state2 or X) begin 
            case(state2)
            S3:begin if(X) next_state2<=S4;
                      else next_state2<=SB;end
            S4:begin if(X) next_state2<=SB;
                      else next_state2<=S5;end
            S5:begin if(X) next_state2<=SB;
                      else next_state2<=S3;end
            SB:begin if(!X)
                        begin
                            if(state1==S2)
                            next_state2<=S3;
                            else next_state2<=SB;end
                            else next_state2<=SB;
                        end
             endcase
             end
        assign Z = (state2 == S5)?1:0;
endmodule