1題目說(shuō)明

在許多（較舊的）串行通信協(xié)議中，每個(gè)數(shù)據(jù)字節(jié)都與一個(gè)起始位和一個(gè)停止位一起發(fā)送，以幫助接收器從位流中分隔字節(jié)。一種常見(jiàn)的方案是使用一個(gè)起始位 (0)、8 個(gè)數(shù)據(jù)位和 1 個(gè)停止位 (1)。當(dāng)沒(méi)有傳輸任何內(nèi)容（空閑）時(shí)，該線(xiàn)路也處于邏輯 1。

設(shè)計(jì)一個(gè)有限狀態(tài)機(jī)，當(dāng)給定比特流時(shí)，該機(jī)器將識(shí)別何時(shí)正確接收了字節(jié)。它需要識(shí)別起始位，等待所有 8 個(gè)數(shù)據(jù)位，然后驗(yàn)證停止位是否正確。如果停止位沒(méi)有按預(yù)期出現(xiàn)，則 FSM 必須等到它找到停止位，然后才能?chē)L試接收下一個(gè)字節(jié)。

一些時(shí)序圖

無(wú)錯(cuò)誤：

未找到停止位。第一個(gè)字節(jié)被丟棄：

模塊端口聲明

moduletop_module(
inputclk,
inputin,
inputreset,//Synchronousreset
outputdone
);

2題目解析

串口接收問(wèn)題，題目沒(méi)給狀態(tài)圖，需要自己繪制：

moduletop_module(
inputlogicclk,
inputlogicin,
inputlogicreset,//Synchronousreset
outputlogicdone
);

//definestate
typedefenumlogic[3:0]{idle=4'd0,start=4'd1,
receive_1=4'd2,receive_2=4'd3,
receive_3=4'd4,receive_4=4'd5,
receive_5=4'd6,receive_6=4'd7,
receive_7=4'd8,receive_8=4'd9,
stop=4'd10,waite=4'd11
}state_def;

state_defcur_state,next_state;

varlogic[3:0]state_cout;
//describestatetransitionlogicusecombinationallogic

always_combbegin
case(cur_state)
idle:begin
if(!in)begin
next_state=start;
end
elsebegin
next_state=idle;
end
end

start:begin
next_state=receive_1;
end

receive_1:begin
next_state=receive_2;
end

receive_2:begin
next_state=receive_3;
end

receive_3:begin
next_state=receive_4;
end

receive_4:begin
next_state=receive_5;
end

receive_5:begin
next_state=receive_6;
end

receive_6:begin
next_state=receive_7;
end

receive_7:begin
next_state=receive_8;
end

receive_8:begin
if(!in)begin
next_state=waite;
end
elsebegin
next_state=stop;
end
end

stop:begin
if(!in)begin
next_state=start;
end
elsebegin
next_state=idle;
end
end

waite:begin
if(!in)begin
next_state=waite;
end
elsebegin
next_state=idle;
end
end
default:begin
next_state=idle;
end
endcase
end

//descibestatesequencerusesequentiallogic

always_ff@(posedgeclk)begin
if(reset)begin
cur_state<=?idle?;
????end????
????else?begin
????????cur_state?<=?next_state?;
????end
end


//describe?output?decoder?use?combinational?logic

assign?done?=?(cur_state?==?stop)?;?

endmodule

點(diǎn)擊Submit，等待一會(huì)就能看到下圖結(jié)果：

注意圖中無(wú)波形。

這一題就結(jié)束了。

Part3Problem 135-Fsm_serialdata

3題目說(shuō)明

上一題用一個(gè)有限狀態(tài)機(jī)可以識(shí)別串行比特流中的字節(jié)何時(shí)被正確接收，添加一個(gè)數(shù)據(jù)路徑將輸出正確接收的數(shù)據(jù)字節(jié)。out_byte在done為1時(shí)需要有效，否則不關(guān)心。

請(qǐng)注意，串行協(xié)議首先發(fā)送最低有效位。

一些時(shí)序圖

無(wú)錯(cuò)誤：

模塊端口聲明

moduletop_module(
inputclk,
inputin,
inputreset,//Synchronousreset
output[7:0]out_byte,
outputdone
);

4題目解析

狀態(tài)機(jī)與上題一致。

moduletop_module(
inputlogicclk,
inputlogicin,
inputlogicreset,//Synchronousreset
output[7:0]out_byte,
outputlogicdone
);

//definestate
typedefenumlogic[3:0]{idle=4'd0,start=4'd1,
receive_1=4'd2,receive_2=4'd3,
receive_3=4'd4,receive_4=4'd5,
receive_5=4'd6,receive_6=4'd7,
receive_7=4'd8,receive_8=4'd9,
stop=4'd10,waite=4'd11
}state_def;

state_defcur_state,next_state;

varlogic[3:0]state_cout;
//describestatetransitionlogicusecombinationallogic

always_combbegin
case(cur_state)
idle:begin
if(!in)begin
next_state=start;
end
elsebegin
next_state=idle;
end
end

start:begin
next_state=receive_1;
end

receive_1:begin
next_state=receive_2;
end

receive_2:begin
next_state=receive_3;
end

receive_3:begin
next_state=receive_4;
end

receive_4:begin
next_state=receive_5;
end

receive_5:begin
next_state=receive_6;
end

receive_6:begin
next_state=receive_7;
end

receive_7:begin
next_state=receive_8;
end

receive_8:begin
if(!in)begin
next_state=waite;
end
elsebegin
next_state=stop;
end
end

stop:begin
if(!in)begin
next_state=start;
end
elsebegin
next_state=idle;
end
end

waite:begin
if(!in)begin
next_state=waite;
end
elsebegin
next_state=idle;
end
end
default:begin
next_state=idle;
end
endcase
end

//descibestatesequencerusesequentiallogic

always_ff@(posedgeclk)begin
if(reset)begin
cur_state<=?idle?;
????end????
????else?begin
????????cur_state?<=?next_state?;
????end
end


//describe?output?decoder?use?combinational?logic

assign?done?=?(cur_state?==?stop)?;
assign?out_byte?=?done???out_bytes_temp?:?8'd0?;

var?logic?[7:0]?out_bytes_temp?;
always_ff?@(?posedge?clk?)?begin?
????if?(next_state?==?receive_1)?begin
????????out_bytes_temp[0]?<=?in?;
????end
????else?if?(next_state?==?receive_2)?begin
????????out_bytes_temp[1]?<=?in?;
????end
????else?if?(next_state?==?receive_3)?begin
????????out_bytes_temp[2]?<=?in?;
????end
????else?if?(next_state?==?receive_4)?begin
????????out_bytes_temp[3]?<=?in?;
????end?
????else?if?(next_state?==?receive_5)?begin
????????out_bytes_temp[4]?<=?in?;
????end
????else?if?(next_state?==?receive_6)?begin
????????out_bytes_temp[5]?<=?in?;
????end
????else?if?(next_state?==?receive_7)?begin
????????out_bytes_temp[6]?<=?in?;
????end
????else?if?(next_state?==?receive_8)?begin
????????out_bytes_temp[7]?<=?in?;
????end
????
end

endmodule

點(diǎn)擊Submit，等待一會(huì)就能看到下圖結(jié)果：

注意圖中無(wú)波形。

這一題就結(jié)束了。

Part4Problem 136-Fsm_serialdp

5題目說(shuō)明

這題仍然是在前面的基礎(chǔ)上進(jìn)行進(jìn)化，增添了奇偶校驗(yàn)位。奇偶校驗(yàn)(Parity Check)是一種校驗(yàn)代碼傳輸正確性的方法。根據(jù)被傳輸?shù)囊唤M二進(jìn)制代碼的數(shù)位中“1”的個(gè)數(shù)是奇數(shù)或偶數(shù)來(lái)進(jìn)行校驗(yàn)。采用奇數(shù)的稱(chēng)為奇校驗(yàn)，反之，稱(chēng)為偶校驗(yàn)。奇偶校驗(yàn)是在傳輸中保障數(shù)據(jù)接收正確的常用方法，也是最初級(jí)的校驗(yàn)方式。

該題采用的是奇校驗(yàn)的方式，并且提供了奇偶校驗(yàn)?zāi)K。原本 start 和 stop 位之間的8 bit 變?yōu)榱? bit，新增的1 bit 為奇校驗(yàn)位，從而使得這9 bit 中“1”的數(shù)量為奇數(shù)個(gè)，即題目中提供的奇偶校驗(yàn)?zāi)K輸出為1時(shí)表面數(shù)據(jù)正確，否則數(shù)據(jù)錯(cuò)誤不予接收。波形圖如下所示。

moduleparity(
inputclk,
inputreset,
inputin,
outputregodd);

always@(posedgeclk)
if(reset)odd<=?0;
????????else?if?(in)?odd?<=?~odd;

endmodule

請(qǐng)注意，串行協(xié)議首先發(fā)送最低有效位，然后在 8 個(gè)數(shù)據(jù)位之后發(fā)送奇偶校驗(yàn)位。

一些時(shí)序圖

模塊端口聲明

moduletop_module(
inputclk,
inputin,
inputreset,//Synchronousreset
output[7:0]out_byte,
outputdone
);

6題目解析

moduletop_module(
inputlogicclk,
inputlogicin,
inputlogicreset,//Synchronousreset
output[7:0]out_byte,
outputlogicdone
);


//ModifyFSManddatapathfromFsm_serialdata

//definestate
typedefenumlogic[3:0]{idle=4'd0,start=4'd1,
receive_1=4'd2,receive_2=4'd3,
receive_3=4'd4,receive_4=4'd5,
receive_5=4'd6,receive_6=4'd7,
receive_7=4'd8,receive_8=4'd9,
stop=4'd10,waite=4'd11,parity=4'd12
}state_def;

state_defcur_state,next_state;

wirelogicodd;
//describestatetransitionlogicusecombinationallogic

always_combbegin
case(cur_state)
idle:begin
if(!in)begin
next_state=start;
end
elsebegin
next_state=idle;
end
end

start:begin
next_state=receive_1;
end

receive_1:begin
next_state=receive_2;
end

receive_2:begin
next_state=receive_3;
end

receive_3:begin
next_state=receive_4;
end

receive_4:begin
next_state=receive_5;
end

receive_5:begin
next_state=receive_6;
end

receive_6:begin
next_state=receive_7;
end

receive_7:begin
next_state=receive_8;
end

receive_8:begin
next_state=parity;
end

parity:begin
if(!in)begin
next_state=waite;
end
elsebegin
next_state=stop;
end
end

stop:begin
if(!in)begin
next_state=start;
end
elsebegin
next_state=idle;
end
end

waite:begin
if(!in)begin
next_state=waite;
end
elsebegin
next_state=idle;
end
end

default:begin
next_state=idle;
end
endcase
end

//descibestatesequencerusesequentiallogic

always_ff@(posedgeclk)begin
if(reset)begin
cur_state<=?idle?;
????end????
????else?begin
????????cur_state?<=?next_state?;
????end
end


//describe?output?decoder?use?combinational?logic

assign?reset_en?=?(reset?==?1'd1)?||?(next_state?==?stop)?||?(next_state?==?idle)?||?(next_state?==?start)?;

wire?logic?reset_en?;
var?logic?[7:0]?out_bytes_temp?;
always_ff?@(?posedge?clk?)?begin?
????if?(next_state?==?receive_1)?begin
????????out_bytes_temp[0]?<=?in?;
????end
????else?if?(next_state?==?receive_2)?begin
????????out_bytes_temp[1]?<=?in?;
????end
????else?if?(next_state?==?receive_3)?begin
????????out_bytes_temp[2]?<=?in?;
????end
????else?if?(next_state?==?receive_4)?begin
????????out_bytes_temp[3]?<=?in?;
????end?
????else?if?(next_state?==?receive_5)?begin
????????out_bytes_temp[4]?<=?in?;
????end
????else?if?(next_state?==?receive_6)?begin
????????out_bytes_temp[5]?<=?in?;
????end
????else?if?(next_state?==?receive_7)?begin
????????out_bytes_temp[6]?<=?in?;
????end
????else?if?(next_state?==?receive_8)?begin
????????out_bytes_temp[7]?<=?in?;
????end
????
end

always_ff?@(?posedge?clk?)?begin?
????if?(reset)?begin
????????out_byte?<=?8'd0?;
????????done?<=?1'd0?;
????end
????else?if?(next_state?==?stop?&&?odd?==?1'd1)?begin
????????out_byte?<=?out_bytes_temp?;
????????done?<=?1'd1?;
????end
????else?begin
????????out_byte?<=?8'd0?;
????????done?<=?1'd0?;
????end
????
end

???//?New:?Add?parity?checking.?

parity?u_parity?(?.clk(clk),
??????????????????.reset(reset_en),
??????????????????.in(in),
??????????????????.odd(odd)
????????????????);

????

endmodule

點(diǎn)擊Submit，等待一會(huì)就能看到下圖結(jié)果：

注意圖中無(wú)波形。

這一題就結(jié)束了。

Part5Problem 137-Fsm_hdlc

7題目說(shuō)明

同步HDLC幀涉及從連續(xù)的比特流中解碼尋找某一幀(即數(shù)據(jù)包)的開(kāi)始和結(jié)束位置的位模式。(對(duì)位模式不太理解的可以參見(jiàn)https://zhuanlan.zhihu.com/p/46317118)。如果接收到連續(xù)的6個(gè)1(即01111110)，即是幀邊界的“標(biāo)志”。同時(shí)為了避免輸入的數(shù)據(jù)流中意外包含這個(gè)幀邊界“標(biāo)志”，數(shù)據(jù)的發(fā)送方必須在數(shù)據(jù)中連續(xù)的5個(gè)1之后插入一個(gè)0，而數(shù)據(jù)的接收方必須將這個(gè)多余的0檢測(cè)出來(lái)并丟棄掉。同時(shí)，如果輸入檢測(cè)到了了連續(xù)7個(gè)或更多的1時(shí)，接收方還需要發(fā)出錯(cuò)誤信號(hào)。

創(chuàng)建一個(gè)有限狀態(tài)機(jī)來(lái)識(shí)別這三個(gè)序列：

0111110 : 信號(hào)位需要被丟棄（disc）。

01111110：標(biāo)記幀的開(kāi)始/結(jié)束 ( flag )。

01111111...：錯(cuò)誤（7 個(gè)或更多 1）（錯(cuò)誤）。

當(dāng) FSM 被重置時(shí)，它應(yīng)該處于一種狀態(tài)，就像之前的輸入為 0 一樣。

以下是說(shuō)明所需操作的一些示例序列。

丟棄0111110：

圖片來(lái)自HDLBits

標(biāo)志01111110：

圖片來(lái)自HDLBits

重置和錯(cuò)誤01111111...：

圖片來(lái)自HDLBits

實(shí)現(xiàn)這個(gè)狀態(tài)機(jī)。

模塊端口聲明

moduletop_module(
inputclk,
inputreset,//Synchronousreset
inputin,
outputdisc,
outputflag,
outputerr);

8題目解析

1、請(qǐng)使用10個(gè)狀態(tài)以?xún)?nèi)的摩爾機(jī)。

2、狀態(tài)圖：

moduletop_module(
inputlogicclk,
inputlogicreset,//Synchronousreset
inputlogicin,
outputlogicdisc,
outputlogicflag,
outputlogicerr
);

//definestate
typedefenumlogic[2:0]{detect_0=3'd0,receive_1=3'd1,
receive_2=3'd2,receive_3=3'd3,
receive_4=3'd4,receive_5=3'd5,
receive_6=3'd6,receive_7=3'd7
}state_def;

state_defcur_state,next_state;

//describestatetransitionlogicusecombinationallogic
always_combbegin
case(cur_state)
detect_0:begin
next_state=in?receive_1:detect_0;
end

receive_1:begin
next_state=in?receive_2:detect_0;
end

receive_2:begin
next_state=in?receive_3:detect_0;
end

receive_3:begin
next_state=in?receive_4:detect_0;
end

receive_4:begin
next_state=in?receive_5:detect_0;
end

receive_5:begin
next_state=in?receive_6:detect_0;
end

receive_6:begin
next_state=in?receive_7:detect_0;
end

receive_7:begin
next_state=in?receive_7:detect_0;
end

default:begin
next_state=detect_0;
end
endcase
end

//describestatesequecerusesequentiallogic

always_ff@(posedgeclk)begin
if(reset)begin
cur_state<=?detect_0?;
????????end
????????else?begin
????????????cur_state?<=?next_state?;
????????end
????end

????//describe?output?decoder?use?sequential?and?combinational?logic

????always_ff?@(?posedge?clk?)?begin?
????????if?(reset)?begin
????????????disc?<=?1'd0?;
????????????flag?<=?1'd0?;
????????end
????????else?begin
????????????case?(1'd1)
????????????????(cur_state?==?receive_5)?&&?(next_state?==?detect_0):?disc?<=?1'd1?;
????????????????(cur_state?==?receive_6)?&&?(next_state?==?detect_0):?flag?<=?1'd1?;
????????????????default?:?begin
????????????????????disc?<=?1'd0?;
????????????????????flag?<=?1'd0?;
????????????????end
????????????endcase
????????end
????end

????assign?err??=?(cur_state?==?receive_7)?;

endmodule

點(diǎn)擊Submit，等待一會(huì)就能看到下圖結(jié)果：

注意圖中無(wú)波形。

這一題就結(jié)束了。

Part6Problem 138-ece241_2013_q8

9題目說(shuō)明

設(shè)計(jì)一個(gè)單輸入單輸出串行 2 的互補(bǔ)摩爾狀態(tài)機(jī)。輸入 (x) 是一系列位（每個(gè)時(shí)鐘周期一個(gè)），從數(shù)字的最低有效位開(kāi)始，輸出 (Z) 是輸入的 2 的補(bǔ)碼。機(jī)器將接受任意長(zhǎng)度的輸入數(shù)字。該電路需要異步復(fù)位。轉(zhuǎn)換在Reset釋放時(shí)開(kāi)始，在Reset置位時(shí)停止。

例如：

模塊端口聲明

moduletop_module(
inputclk,
inputareset,
inputx,
outputz
);

10題目解析

米里型的輸出由當(dāng)前狀態(tài)和輸入信號(hào)的組合邏輯實(shí)現(xiàn)，輸出信號(hào)與輸入信號(hào)同步。

而摩爾型狀態(tài)機(jī)的輸出僅由當(dāng)前狀態(tài)決定，與輸入信號(hào)異步，往往存在延遲。

moduletop_module(
inputlogicclk,
inputlogicaresetn,//Asynchronousactive-lowreset
inputlogicx,
outputlogicz);

//definestate
typedefenumlogic[1:0]{idle=2'd0,state_1=2'd1,state_2=2'd2}state_def;

state_defcur_state,next_state;

//describestatesequecerusesequentiallogic
always_ff@(posedgeclkornegedgearesetn)begin
if(!aresetn)begin
cur_state<=?idle?;
????????end
????????else?begin
????????????cur_state?<=?next_state?;
????????end
????end

????//describe?state?transition?logic?use?combinational?logic

????always_comb?begin?
????????case?(cur_state)
????????????idle:?begin
????????????????next_state?=?x???state_1?:?idle?;
????????????end?

????????????state_1:?begin
????????????????next_state?=?x???state_1?:?state_2?;
????????????end

????????????state_2:?begin
????????????????next_state?=?x???state_1?:?idle?;
????????????end
????????????default:?begin
????????????????next_state?=?idle?;
????????????end
????????endcase
????end

????//describe?output?decoder?use?combinational?logic
????assign?z?=?(cur_state?==?state_2)?&&?(x?==?1'd1)?;
????
endmodule

點(diǎn)擊Submit，等待一會(huì)就能看到下圖結(jié)果：

注意圖中的Ref是參考波形，Yours是你的代碼生成的波形，網(wǎng)站會(huì)對(duì)比這兩個(gè)波形，一旦這兩者不匹配，仿真結(jié)果會(huì)變紅。

這一題就結(jié)束了。

Part7Problem 139-ece241_2014_q5a

11題目說(shuō)明

設(shè)計(jì)一個(gè)單輸入單輸出串行 2 的互補(bǔ)摩爾狀態(tài)機(jī)。輸入 (x) 是一系列位（每個(gè)時(shí)鐘周期一個(gè)），從數(shù)字的最低有效位開(kāi)始，輸出 (Z) 是輸入的 2 的補(bǔ)碼。機(jī)器將接受任意長(zhǎng)度的輸入數(shù)字。該電路需要異步復(fù)位。轉(zhuǎn)換在Reset釋放時(shí)開(kāi)始，在Reset置位時(shí)停止。

例如：

圖片來(lái)自HDLBits

模塊端口聲明

moduletop_module(
inputclk,
inputareset,
inputx,
outputz
);

12題目解析

moduletop_module(
inputlogicclk,
inputlogicareset,
inputlogicx,
outputlogicz
);

//definestate

typedefenumlogic[1:0]{S0=2'd0,S1=2'd1,S2=2'd2}state_def;

state_defcur_state,next_state;

//describestatetransitionusecombinationallogic

always_combbegin
case(cur_state)
S0:begin
next_state=x?S1:S0;
end

S1:begin
next_state=x?S2:S1;
end

S2:begin
next_state=x?S2:S1;
end
default:begin
next_state=S0;
end
endcase
end

//describestatesequencerusesequentiallogic

always_ff@(posedgeclkorposedgeareset)begin
if(areset)begin
cur_state<=?S0?;
????end
????else?begin
????????cur_state?<=?next_state?;
????end
end


//describe?output?decoder?use?combinational?logic

assign?z?=?(cur_state?==?S1)?;
?
endmodule

點(diǎn)擊Submit，等待一會(huì)就能看到下圖結(jié)果：

注意圖中的Ref是參考波形，Yours是你的代碼生成的波形，網(wǎng)站會(huì)對(duì)比這兩個(gè)波形，一旦這兩者不匹配，仿真結(jié)果會(huì)變紅。

這一題就結(jié)束了。

Part8Problem 140-23_ece241_2014_q5b

13題目說(shuō)明

本題和上一題 Serial two's complementer (Moore FSM) 一樣，使用狀態(tài)機(jī)實(shí)現(xiàn)一個(gè)二進(jìn)制補(bǔ)碼生成器，不同的是此題使用米里型狀態(tài)機(jī)實(shí)現(xiàn)。

圖片來(lái)自HDLBits

模塊端口聲明

moduletop_module(
inputclk,
inputareset,
inputx,
outputz
);

14題目解析

存在兩個(gè)狀態(tài)，復(fù)位狀態(tài) A，在輸入 x 為 1 后狀態(tài)轉(zhuǎn)移為 B，并保持在狀態(tài) B。

狀態(tài) A 中輸出 z 與輸入 x 相同；狀態(tài) B 中輸出 z 與輸入 x 相反。

moduletop_module(
inputlogicclk,
inputlogicareset,
inputlogicx,
outputlogicz
);

//definestate

typedefenumlogic{S0=1'd0,S1=1'd1}state_def;

state_defcur_state,next_state;

//describestatetransitionusecombinationallogic

always_combbegin
case(cur_state)
S0:begin
next_state=x?S1:S0;
end

S1:begin
next_state=S1;
end

default:begin
next_state=S0;
end
endcase
end

//describestatesequencerusesequentiallogic

always_ff@(posedgeclkorposedgeareset)begin
if(areset)begin
cur_state<=?S0?;
????end
????else?begin
????????cur_state?<=?next_state?;
????end
end


//describe?output?decoder?use?combinational?logic

assign?z?=?((cur_state?==?S0)?&&?(x?==?1'd1))?||?((cur_state?==?S1?)?&&?(x?==?1'd0));
?
endmodule

點(diǎn)擊Submit，等待一會(huì)就能看到下圖結(jié)果：

注意圖中的Ref是參考波形，Yours是你的代碼生成的波形，網(wǎng)站會(huì)對(duì)比這兩個(gè)波形，一旦這兩者不匹配，仿真結(jié)果會(huì)變紅。

這一題就結(jié)束了。

Part9Problem 141-2014_q3fsm

15題目說(shuō)明

考慮具有輸入s和w的有限狀態(tài)機(jī)。假設(shè) FSM 開(kāi)始于稱(chēng)為A的重置狀態(tài)，如下所示。只要s = 0， FSM 就保持在狀態(tài)A ，當(dāng)s = 1 時(shí)，它會(huì)移動(dòng)到狀態(tài)B。一旦進(jìn)入狀態(tài)B，F(xiàn)SM在接下來(lái)的三個(gè)時(shí)鐘周期內(nèi)檢查輸入w的值。如果在這些時(shí)鐘周期中恰好有兩個(gè)時(shí)鐘周期內(nèi)w = 1，則 FSM 必須 在下一個(gè)時(shí)鐘周期內(nèi)將輸出z設(shè)置為 1。否則z必須為 0。FSM 繼續(xù)檢查w對(duì)于接下來(lái)的三個(gè)時(shí)鐘周期，依此類(lèi)推。下面的時(shí)序圖說(shuō)明了不同w值所需的z值。

使用盡可能少的狀態(tài)。請(qǐng)注意，s輸入僅在狀態(tài)A中使用，因此只需考慮w輸入。

圖片來(lái)自HDLBits

模塊端口聲明

moduletop_module(
inputclk,
inputreset,//Synchronousreset
inputs,
inputw,
outputz
);

16題目解析

值得注意的是：需要三個(gè)周期中 exactly 兩個(gè)周期為 1 。

moduletop_module(
inputlogicclk,
inputlogicreset,//Synchronousreset
inputlogics,
inputlogicw,
outputlogicz
);

//definestate

typedefenumlogic{A=1'd0,B=1'd1}state_def;

state_defcur_state,next_state;

//describestatetransitionusecombinationallogic

always_combbegin
case(cur_state)
A:begin
next_state=s?B:A;
end

B:begin
next_state=B;
end

default:begin
next_state=A;
end
endcase
end

//describestatesequencerusesequentiallogic

always_ff@(posedgeclk)begin
if(reset)begin
cur_state<=?A?;
????end
????else?begin
????????cur_state?<=?next_state?;
????end
end

//define?counter?use?sequential?and?combinational?logic

var?logic?[1:0]?count?,?count_c;

wire?logic?resetn?;

assign?resetn?=?(count_c?==?2'd3)???1'd0?:?1'd1?;

always_ff?@(?posedge?clk?)?begin?
????if(reset)?begin
????????count?<=?2'd0?;
????end
????else?if?(!resetn)?begin
????????????if(w?==?1'd1)?begin
?????????????count?<=?2'd1?;
????????????end
????????????else?begin
????????????count?<=?2'd0?;
????????????end
????end
????else?begin
????????if?(cur_state?==?B?&&?w?==?1'd1)?begin
????????????count?<=?count?+?2'd1?;
????????end
????????else?begin
????????????count?<=?count?;
????????end
????????
????end
end

always_ff?@(?posedge?clk?)?begin?
????if?(reset)?begin
????????count_c?<=?2'd0?;
????end
????else?begin
????????if?(cur_state?==?B?&&?count_c?==?2'd3)?begin
????????count_c?<=?2'd1?;
????????end
????????else?if?(cur_state?==?B)?begin
????????????count_c?<=?count_c?+?2'd1?;
????????end
????????else?begin
????????count_c?<=?count_c?;
????????end
????end
????
end


//describe?output?decoder?use?combinational?logic

always_ff@(posedge?clk)?begin?
????if(reset)?begin
????????z?<=?1'd0?;
????end
????else?begin
??????case(?1'd1?)
??????(cur_state?==?B?&&?count_c?==?2'd2?&&?count?==?1?&&?w?==?1)?:?begin
????????z?<=?1'd1?;
??????end
??????(cur_state?==?B?&&?count_c?==?2'd2?&&?count?==?2?&&?w?==?0)?:?begin
????????z?<=?1'd1?;
??????end
??????default?:?begin
????????z?<=?1'd0?;
??????end
??????endcase
????end
end

endmodule

點(diǎn)擊Submit，等待一會(huì)就能看到下圖結(jié)果：

注意圖中無(wú)波形。

這一題就結(jié)束了。

Part10Problem 142-2014_q3bfsm

17題目說(shuō)明

這是一道簡(jiǎn)單的根據(jù)狀態(tài)轉(zhuǎn)移實(shí)現(xiàn)狀態(tài)機(jī)的題目，實(shí)現(xiàn)完整的三段式狀態(tài)機(jī)

圖片來(lái)自HDLBits

模塊端口聲明

moduletop_module(
inputclk,
inputreset,//Synchronousreset
inputx,
outputz
);

18題目解析

moduletop_module(
inputlogicclk,
inputlogicreset,//Synchronousreset
inputlogicx,
outputlogicz
);

//definestate

typedefenumlogic[2:0]{S0=3'b000,S1=3'b001,
S2=3'b010,S3=3'b011,
S4=3'b100
}state_def;

state_defcur_state,next_state;

//describestatetransitionusecombinationallogic

always_combbegin
case(cur_state)
S0:begin
next_state=x?S1:S0;
end

S1:begin
next_state=x?S4:S1;
end

S2:begin
next_state=x?S1:S2;
end

S3:begin
next_state=x?S2:S1;
end

S4:begin
next_state=x?S4:S3;
end

default:begin
next_state=S0;
end
endcase
end

//describestatesequencerusesequentiallogic

always_ff@(posedgeclk)begin
if(reset)begin
cur_state<=?S0?;
????end
????else?begin
????????cur_state?<=?next_state?;
????end
end


//describe?output?decoder?use?combinational?logic

assign?z?=?(cur_state?==?S3)?||?(cur_state?==?S4)?;

endmodule

點(diǎn)擊Submit，等待一會(huì)就能看到下圖結(jié)果：

注意圖中無(wú)參考波形。

這一題就結(jié)束了。

Part11總結(jié)

今天的幾道題就結(jié)束了，對(duì)于狀態(tài)機(jī)的理解還是有益處的，三段式狀態(tài)機(jī)是題目一直推崇的，類(lèi)似狀態(tài)機(jī)的公示，可以“套”進(jìn)去。

審核編輯：劉清